1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to the formation of semiconductor structures comprising a first substrate and a second substrate having a different orientation.
2. Description of the Related Art
Integrated circuits comprise a large number of individual circuit elements, e.g., transistors, capacitors and resistors. These elements are connected to form complex circuits, such as memory devices, logic devices and microprocessors. The performance of integrated circuits can be improved by increasing the number of functional elements per circuit in order to increase the circuit's functionality and/or by increasing the speed of operation of the circuit elements. A reduction of feature sizes allows the formation of a greater number of circuit elements on the same area, hence increasing the functionality of the circuit, and also reducing signal propagation delays, thus making an increase of the speed of operation of circuit elements possible.
Field effect transistors are typically used as switching elements in integrated circuits. They provide a means to control a current flowing through a channel region located between a source region and a drain region. The source region and the drain region are highly doped. In N-type transistors, the source and drain regions are doped with an N-type dopant. Conversely, in P-type transistors, the source and drain regions are doped with a P-type dopant. The doping of the channel region is inverse to the doping of the source region and the drain region. The conductivity of the channel region is controlled by a gate voltage applied to a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. Depending on the gate voltage, the channel region may be switched between a conductive “on” state and a substantially non-conductive “off” state.
When reducing the size of field effect transistors, it is important to maintain a high conductivity of the channel region in the “on” state. The conductivity of the channel region in the “on” state depends on the dopant concentration in the channel region, the mobility of the charge carriers, the extension of the channel region in the width direction of the transistor and on the distance between the source region and the drain region, which is commonly denoted as “channel length.” While a reduction of the width of the channel region leads to a decrease of the channel conductivity, a reduction of the channel length enhances the channel conductivity. An increase of the charge carrier mobility leads to an increase of the channel conductivity.
As feature sizes are reduced, the extension of the channel region in the width direction is also reduced. A reduction of the channel length entails a plurality of issues associated therewith. First, advanced techniques of photolithography and etching have to be provided in order to reliably and reproducibly create transistors having short channel lengths. Moreover, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the source region and in the drain region in order to provide a low sheet resistivity and a low contact resistivity in combination with a desired channel controllability.
In view of the problems associated with a further reduction of the channel length, it has been proposed to also enhance the performance of field effect transistors by increasing the charge carrier mobility in the channel region. In principle, at least three approaches may be used to increase the charge carrier mobility.
First, the dopant concentration in the channel region may be reduced. Thus, the probability of scattering events of charge carriers in the channel region is reduced, which leads to an increase of the conductivity of the channel region. Reducing the dopant concentration in the channel region, however, significantly affects the threshold voltage of the transistor device. This makes the reduction of dopant concentration a less attractive approach.
Second, the lattice structure in the channel region may be modified by creating tensile or compressive stress. This leads to a modified mobility of electrons and holes, respectively. Depending on the magnitude of the stress, a compressive stress may significantly increase the mobility of holes in a silicon layer, and may also increase the electron mobility. The mobility of electrons may also be increased by providing a silicon layer having a tensile stress.
Third, the mobility of electrons and holes in the channel region of a field effect transistor may depend on the orientation of the length direction of the channel relative to the crystal lattice of a substrate wherein the channel region is formed. It has been found that, in N-type field effect transistors, a relatively high mobility of electrons may be obtained if the transistors are formed on an {001} surface of a silicon substrate. In P-type field effect transistors, however, a greater mobility of the holes in the channel region may be obtained if the transistors are formed on an {011} surface of a silicon substrate. Therefore, it has been proposed to form an integrated circuit in a semiconductor structure comprising a first and a second substrate, wherein surfaces of the first and the second substrate on which field effect transistors are formed are oriented differently with respect to the crystal lattice of the respective substrate. This approach, which may also be combined with a reduction of the dopant concentration in the channel region and/or a provision of stress in the channel region, is commonly denoted as “hybrid orientation technique.”
An example of a method of manufacturing a semiconductor structure according to the state of the art employing hybrid orientation technique is described with reference to FIGS. 1a-1c. FIG. 1a shows a schematic cross-sectional view of a semiconductor structure 100 in a first stage of the manufacturing process according to the state of the art. The semiconductor structure 100 comprises a first substrate 101. The first substrate 101 comprises a surface 130 on which a layer 102 comprised of an electrically insulating material, such as silicon dioxide and/or silicon nitride, is formed. The first substrate 101 may be comprised of crystalline silicon and the surface 130 can be substantially a {001} surface.
A second substrate 103 is provided. The second substrate 103 may be comprised of the same material as the first substrate 101, for example crystalline silicon, and has a surface 131, the orientation of which relative to the crystal lattice of the second substrate is different from the orientation of the surface 130 relative to the crystal lattice of the first substrate 101. In examples of methods according to the state of the art wherein the surface 130 is substantially a {001} surface, the surface 131 can be substantially a {011} surface. The second substrate 103 is bonded to the first substrate 101. This can be done by means of wafer bonding techniques well known to persons skilled in the art, such as anodic bonding.
FIG. 1b shows a schematic cross-sectional view of the semiconductor structure 100 in a later stage of the manufacturing process. After bonding the second substrate 103 to the first substrate 101, a portion of the second substrate 103 is removed to obtain a smaller thickness of the second substrate 103. This can be done by cleaving the second substrate 103.
An implantation of hydrogen into the second substrate 103 may be performed before bonding the second substrate 103 to the first substrate 101. To this end, the surface 131 can be irradiated with hydrogen ions. The hydrogen ions penetrate the second substrate 103 and are stopped at a depth which may depend on the energy of the ions and their angle of incidence. Then, the ions are neutralized and incorporated into the second substrate 103. Ion energy and/or angle of incidence are adapted such that a moderately large amount of hydrogen is incorporated at a depth corresponding to the desired thickness of the portion of the second substrate 103 remaining on the first substrate. The presence of hydrogen reduces the mechanical stability of the second substrate 103. The cleaving process may, for example, be performed by directing a high pressure water jet to the semiconductor structure 100. Thereby, the second substrate 103 breaks apart at the depth to which the hydrogen was implanted.
When the second substrate 103 is cleaved, a surface 140 is formed at the side of the second substrate 103 opposite to the first substrate 101. An orientation of the surface 140 relative to the crystal lattice of the second substrate 103 may correspond to the orientation of the surface 131. For example, the surface 140 may be a {011} silicon surface.
After cleaving the second substrate 103, a trench isolation structure 106 is formed in the semiconductor structure 100. The trench isolation structure 106 provides electrical insulation between a first portion 104 and a second portion 105 of the semiconductor structure 100. In the formation of the trench isolation structure 106, methods of photolithography, etching, oxidation and/or deposition well known to persons skilled in the art may be employed.
Thereafter, a mask layer 107, which may, for example, comprise silicon dioxide, is formed over the second substrate 103. This can be done by means of known deposition processes such as chemical vapor deposition (CVD) and/or plasma enhanced chemical vapor deposition (PECVD). Alternatively, the mask layer 107 may be formed by oxidizing a portion of the second substrate 103 at its surface. The reduction of thickness of the second substrate 103 may be taken into account in advance by correspondingly providing the second substrate 103 with a greater thickness.
In the second portion 105 of the semiconductor structure 100, the mask layer 107, the second substrate 103 and the layer 102 of electrically insulating material are removed. This can be done by means of known techniques of photolithography and etching.
A schematic cross-sectional view of the semiconductor structure 100 in a further stage of the manufacturing process is shown in FIG. 1c. A selective epitaxial growth process is performed in order to form a material layer 122 over the second portion 105 of the semiconductor structure 100. As persons skilled in the art know, selective epitaxial growth is a variant of plasma enhanced chemical vapor deposition wherein parameters of the deposition process are adapted such that material is deposited only on the surface 130 of the first substrate 101 exposed in the second portion 105 of the semiconductor structure 100, whereas substantially no material deposition occurs on the surface of the trench isolation structure 106 and the mask layer 107. The material layer 122 may comprise the same material as the first substrate 101. In the formation of the material layer 122, the crystal structure of the material layer 122 adapts to that of the underlying first substrate 101. Therefore, a surface 150 of the material layer 122 has substantially the same orientation as the surface 130 of the first substrate 101.
Then, the mask layer 107 is removed and a first transistor element 110 and a second transistor element 111 are formed in the first 104 and the second 105 portion of the semiconductor structure 100, respectively. This can be done by means of processes well known to persons skilled in the art.
The first transistor element 110 comprises a gate electrode 112 separated from the second substrate 103 by a gate insulation layer 116 and flanked by a sidewall spacer structure 114. Adjacent the gate electrode 112, a source region 118 and a drain region 119 are formed. In examples of manufacturing processes according to the state of the art wherein the surface 140 of the second substrate 103 is a silicon {011} surface, the first transistor element 110 can be a P-type field effect transistor.
Similar to the first transistor element 110, the second transistor element 111 comprises a gate electrode 113 separated from the material layer 122 by a gate insulation layer 117 and flanked by a sidewall spacer structure 115 as well as a source region 120 and a drain region 121. In examples of manufacturing processes according to the state of the art wherein the surface 150 of the material layer 122 is a silicon {001} surface, the second transistor element 111 can be an N-type field effect transistor.
A problem of the method of manufacturing a semiconductor structure according to the state of the art is that the performance of the semiconductor structure 100 may critically depend on the accuracy of alignment of the first transistor element 110 to the crystal lattice of the second substrate 103 and the accuracy of alignment of the second transistor element 111 to the crystal lattice of the material layer 122. The accuracy of alignment of the first transistor element 110 and the second transistor element 111 may depend on the relative orientation of the crystal lattices of the second substrate 103 and the material layer 122, wherein the orientation of the crystal lattice in the material layer 122 is substantially identical to that of the crystal lattice of the first substrate 101. In photolithographic processes and other processes which are performed in the manufacturing of the first transistor element 110 and the second transistor element 111, it may be difficult to compensate any misalignment between the first substrate 101 and the second substrate 103.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.